FPGA designer in VHDL, DO-254 project

$20-$40/hourly

$20-$40/hourly Guru Technology & Programming Overseas
903 days ago

Description

Good knowledge of VHDL is required. Libero Soc and Microsemi will be used The simulator will be Aldec Active-HDL, linting with Aldec Alint Design of a basic control board, standard interfaces, no high…

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